The present invention relates to MIS field effect transistors, and more particularly to MIS field effect transistors having high withstand voltage and to a semiconductor integrated circuit device providing a high withstand voltage MIS field effect transistor.
FIGS. 19 and 20 show the constitution of a conventional high withstand voltage MIS field effect transistors. The high withstand voltage MIS field effect transistor shown in FIG. 19 is a MOSFET produced by the double diffusion process and is called a vertical DMOS since the current just under the gate is caused to flow in a vertical direction in a semiconductor substrate. The high withstand voltage MIS field effect transistor shown in FIG. 20 is a MOSFET produced by the same double diffusion process as in FIG. 19 and is called a horizontal DMOS since the current Just under the gate is caused to flow in a transverse direction in a semiconductor substrate.
The vertical DMOS shown in FIG. 19 is an effective structure as a discrete element, in which an n+-type drain layer 9 has a back surface disposed on a drain electrode 13, an n-type epitaxial layer 20, hereinafter referred to as an "epi layer", is formed on the drain layer 9, and a plurality of p-type base layers 3 are provided on the surface of the epi layer 20. Further, an n+-type source layer 8 is formed in each p-type base layer 3.
Thus, a gate electrode is provided over the epi layer 20 through a pair of source layers 8 and the base layer 3, thereby forming a vertical element. Therefore, when a reverse bias voltage is applied in the vertical DMOS, a depletion layer is extended in the vertical direction. To maintain a sufficient withstand voltage, the impurity concentration of the epi layer 20 should be relatively lowered and the thickness thereof should be sufficient.
On the other hand, a horizontal DMOS (FIG. 20) is formed by using a p-type substrate 1-1. A p type base layer 3-1 is provided on the surface and an n+-type source layer 8-1 is formed in the base layer 3-1 substrate. An n+-type drain layer 9-1 is provided on the same surface off the substrate 1-1 facing the source layer 8-1. The drain layer 9-1 is connected to the base layer 3-1 by an n-type offset layer 18-1 and a gate electrode 7-1 is disposed over the source layer.8-1, the base layer 3-1 and the offset layer 18-1. Thus, when a reverse bias voltage is applied, a depletion layer is extended horizontally in the offset layer 18-1. To maintain the withstand voltage, a long offset layer 18-1 is suitably provided.
A power IC has been developed in which a MOSFET is provided with a withstand voltage of several hundred volts (v) or more and a high current output of several amperes (A) and in which a control circuit portion operates at a low voltage of about 5 V. As disclosed in the Japanese patent publication (kokai) No. 63-314869, an IC for switching power supplies has already been realized.
However, to obtain such power IC at a low cost, miniaturization of chip size is indispensable. Therefore, size reduction of a power MOSFET, which has a large area in a power IC, is important. When the power MOSFET portion is produced, if the production process is increased, reduction of the production cost is difficult, if not impossible.
In the conventional vertical DMOS described above, as previously noted, adequate thickness is needed-to maintain a sufficient withstand voltage. The thickness of the CMOS substrate, etc., of a control circuit portion, can not easily be set to obtain a sufficient withstand voltage. Further, the vertical current flows and the element isolation have to be considered. In this case, since the formation of a buried diffusion layer and epitaxial growth are needed, required man-hours of labor are increased.
On the other hand, in the horizontal DMOS, the depletion layer is laterally extended and a problem of the thickness of the substrate does not occur. Nevertheless, to assure a necessary withstand voltage, a long offset layer is needed. Since assurance of the cross section of the offset layer is difficult, the resistance is easily increased during the on time. Further, since the current is caused to flow in a lateral direction, the carriers are injected into an oxide film formed on the surface of the substrate and are easily changed to hot carriers in a high current density region, whereby failure in the control circuit portion can occur and assurance of reliability of the device is difficult.
Further, in the horizontal DMOS, a field oxide film having a thickness of about a few thousand Angstroms is usually formed between the source and the drain. In this case, in both edge portions of the horizontal DMOS a so called "bird's beak" is concentrated and a residual stress is generated in the formation of the field oxide film. Thus, crystal defects are easily generated. Further, a so called "white ribbon", in which a nitride is stacked in the bird's beak, is generated whereby a withstand voltage for the gate oxide film is remarkably deteriorated. Further, it is well known that the amount of the interface electric charge in the interface between the field oxide film and silicon is large compared to the interface between the gate oxide film and silicon. As a result, the withstand voltage property is disadvantageously deteriorated.